Class 2, Lab 4. P: EET 155. The use of synthesis tools for designing and
building very large-scale integrated (VLSI) circuits. Covers hardware
design language (HDL), simple finite-state machine (FSM) design, and a
CAD/VLSI representation system and Boolean truth tables to minimize and
implement standard logic cells. Use of logic compiling, design simulation,
hardware floorplanning, different layout strategies, pad placement, and
system routing to construct the complete hardware chip.